DS92LV1021_14 Datasheet, PDF (13/23 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

DS92LV1021, DS92LV1210
www.ti.com
SNLS024C – MARCH 1999 – REVISED APRIL 2013
APPLICATION INFORMATION
USING THE DS92LV1021 AND DS92LV1210
The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of
parallel TTL data over a serial Bus LVDS link up to 400 Mbps. Serialization of the input data is accomplished
using an onboard PLL at the Serializer which embeds two clock bits with the data. The Deserializer uses a
separate reference clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data
stream and deserialize the data. The Deserializer monitors the incoming clock information to determine lock
status and will indicate loss of lock by raising the LOCK output.
POWER CONSIDERATIONS
All CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the
constant current source nature of the Bus LVDS outputs minimize the slope of the speed vs. I_CC curve of CMOS
designs.
POWERING UP THE SERIALIZER
The DS92LV1021 must be powered up using a specific sequence to properly start the PLL up. Not following the
sequence can cause the Bus LVDS outputs to be stuck in a certain output state. This may occur if the TCLK
input is driven before power is applied to the Serializer. It is important to note that this is not a latch up condition:
no excessive current is drawn by the Serializer in this state and the power does not need to be cycled to recover
from this state. Cycling the PWRDWN pin from high to low and back to high will reset the PLL and return the
Serializer to normal operation.
To avoid this condition, the Serializer should be powered up (ALL V_CC pins) simultaneously with the PWRDWN
pin held low for 1µs. Do not float the PWRDWN pin, external pull resistor is recommended. Once the V_CC pins
have stabilized the TCLK input can be driven and the Serializer will be ready for data transmission.
POWERING UP THE DESERIALIZER
The DS92LV1210 can be powered up at any time following the proper sequence. The REFCLK input can be
running before the Deserializer is powered up and it must be running in order for the Deserializer to lock to
incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission
at its inputs and locks to the incoming stream. The recommended power up sequence for the deserializer is to
power up all V_CC pins simultaneously with the PWRDWN pin held low for 1µs. Once the V_CC pins have stabilized
the Deserializer is ready for locking. Another option to ensure proper power up is to cycle the PWRDWN pin from
high to low and back to high after power up.
TRANSMITTING DATA
Once the Serializer and Deserializer are powered up and running they must be phase locked to each other in
order to transmit data. Phase locking is accomplished by the Serializer sending SYNC patterns to the
Deserializer. SYNC patterns are sent by the Serializer whenever SYNC1 or SYNC2 inputs are held high. The
LOCK output of the Deserializer is high whenever the Deserializer is not locked. Connecting the LOCK output of
the Deserializer to one of the SYNC inputs of the Serializer will ensure that enough SYNC patterns are sent to
achieve Deserializer lock.
While the Deserializer LOCK output is low, data at the Deserializer outputs (ROUT0-9) is valid except for the
specific case of loss of lock during transmission.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
Serializer: TCLK jitter, V_CC noise (noise bandwidth and out-of-band noise)
Media: ISI, V_CM noise
Deserializer: V_CC noise
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Product Folder Links: DS92LV1021 DS92LV1210