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DS92LV1021_14 Datasheet, PDF (6/23 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
DS92LV1021, DS92LV1210
SNLS024C – MARCH 1999 – REVISED APRIL 2013
Serializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ (1)
Max
tHZD
DO ± HIGH to
See Figure 8 (2)
TRI-STATE Delay
RL = 27Ω,
tLZD
DO ± LOW to TRI-STATE CL=10pF to GND
Delay
3.5
10
2.9
10
tZHD
DO ± TRI-STATE to HIGH
Delay
2.5
10
tZLD
DO ± TRI-STATE to LOW
Delay
2.7
10
tSPW
tPLD
tSD
tBIT
SYNC Pulse Width
Serializer PLL Lock Time
Serializer Delay
Bus LVDS Bit Width
See Figure 9
RL = 27Ω
See Figure 10 RL = 27Ω
RL = 27Ω,
CL=10pF to GND
1024*tTCP
2048*tTCP
tTCP
tTCP + 2.5
tCLK / 12
1029*tTCP
2049*tTCP
tTCP+ 5
(2) Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
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Units
ns
ns
ns
ns
ns
ns
ns
ns
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ (1)
tRFCP
REFCLK Period
tRFDC
REFCLK Duty Cycle
tRFCP / tTCP Ratio of REFCLK to TCLK
Periods
25
T
50
0.83
1
tRFTT
REFCLK Transition Time
3
(1) Typical values are given for VCC = 3.3V and TA = +25°C.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ (1)
tRCP
Receiver out Clock
Period
See Figure 10
tRCP = tTCP
RCLK
25
tCLH
CMOS/TTL Low-to-High CL = 15 pF
Transition Time
See Figure 5
Rout(0-9),
LOCK,
2
tCHL
CMOS/TTL High-to-Low
Transition Time
RCLK
2
tDD
Deserializer Delay
See Figure 11
tROS
ROUT (0-9) Setup Data See Figure 12
to RCLK
RCLK
1.75*tRCP
0.4*tRCP
1.75*tRCP+3
0.5*tRCP
tROH
ROUT (0-9) Hold Data
to RCLK
−0.4*tRCP
−0.5*tRCP
tRDC
RCLK Duty Cycle
tHZR
HIGH to TRI-STATE
See Figure 13
Delay
40
Rout(0-9),
LOCK
50
4+0.5*tRCP
tLZR
LOW to TRI-STATE
Delay
4.2+0.5*tRCP
tZHR
TRI-STATE to HIGH
Delay
6+0.5*tRCP
tZLR
TRI-STATE to LOW
Delay
6.5+0.5*tRCP
Max
Units
62.5
ns
%
1.03
6
ns
Max
62.5
5
5
1.75*tRCP+7
60
10+tRCP
10+tRCP
12+tRCP
12+tRCP
Units
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
(1) Typical values are given for VCC = 3.3V and TA = +25°C.
6
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