AM1705_16 Datasheet, PDF (69/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

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AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
Figure 6-18 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. Refer to
Table 6-21, as an example that shows additional list of commonly-supported SDRAM devices and the
required connections for the address pins. Note that in Table 6-21, page size/column size (not indicated in
the table) is varied to get the required addressability range.
EMIFB
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
SDRAM
2M x 16 x 4
CE
Bank
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
SDRAM Size
64M bits
128M bits
256M bits
512M bits
Figure 6-18. EMIFB to 2M × 16 × 4 bank SDRAM Interface
Table 6-21. Example of 16-bit EMIFB Address Pin Connections
Width
×16
×16
×16
×16
Banks
4
4
4
4
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
SDRAM
EMIFB
Address Pins
A[11:0]
EMB_A[11:0]
A[11:0]
EMB_A[11:0]
A[12:0]
EMB_A[12:0]
A[12:0]
EMB_A[12:0]
6.11.3 EMIFB Registers
Table 6-22 is a list of the EMIFB registers.
BYTE ADDRESS
0xB000 0000
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
Table 6-22. EMIFB Controller Registers
ACRONYM
MIDR
SDCFG
SDRFC
SDTIM1
SDTIM2
SDCFG2
BPRIO
PC1
PC2
PCC
PCMRS
PCT
IRR
REGISTER DESCRIPTION
Module ID Register
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
SDRAM Configuration 2 Register
Peripheral Bus Burst Priority Register
Performance Counter 1 Register
Performance Counter 2 Register
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
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Peripheral Information and Electrical Specifications
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