AM1705_16 Datasheet, PDF (40/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
www.ti.com
6.4 Reset
6.4.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of RTCK/GP7[14]. If an emulator is
driving TCK into the device during reset, then RTCK/GP7[14] will drive out RTCK. If TCK is not being
driven into the device during reset, then RTCK/GP7[14] will drive low.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
. TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
.RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
RTCK/GP7[14] is maintained active through a POR.
A summary of the effects of Power-On Reset is given below:
• All internal logic (including emulation logic and the PLL logic) is reset to its default state
• Internal memory is not maintained through a POR
• All device pins go to a high-impedance state
CAUTION: A watchdog reset triggers a POR.
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Peripheral Information and Electrical Specifications
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