AM1705_16 Datasheet, PDF (141/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

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AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
6.24.1 USB2.0 (USB0) Electrical Data/Timing
The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz,
20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50
ppm maximum.
Table 6-86. Switching Characteristics Over Recommended Operating Conditions for USB2.0 [USB0] (see
Figure 6-48)
No.
PARAMETER
1 t_r(D)
2 t_f(D)
3 t_rfM
4 V_CRS
Rise time, USB0_DP and USB0_DM signals⁽¹⁾
Fall time, USB0_DP and USB0_DM signals⁽¹⁾
Rise/Fall time, matching⁽²⁾
Output signal cross-over voltage⁽¹⁾
5
t_jr(source)NT
Source (Host) Driver jitter, next transition
t_jr(FUNC)NT
6
t_jr(source)PT
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition⁽³⁾
t_jr(FUNC)PT
7
t_w(EOPT)
8
t_w(EOPR)
Function Driver jitter, paired transition
Pulse duration, EOP transmitter ⁽⁴⁾
Pulse duration, EOP receiver ⁽⁴⁾
9
t_(DRATE)
Data Rate
10 Z_DRV
Driver Output Resistance
11 Z_INP
Receiver Input Impedance
(1) Low Speed: C_L = 200 pF, Full Speed: C_L = 50 pF
(2) t_RFM = (t_r/t_f) x 100. [Excluding the first transaction from the Idle state.]
(3) t_jr = t_px(1) - t_px(0)
(4) Must accept as valid EOP
LOW SPEED
1.5 Mbps
MIN
MAX
75
300
75
300
80
120
1.3
2
2
25
1
10
1250
1500
670
1.5
–
–
100k
FULL SPEED
12 Mbps
MIN
MAX
4
20
4
20
90
111
1.3
2
2
2
1
1
160
175
82
12
40.5
49.5
100k
UNIT
ns
ns
%
V
ns
ns
ns
ns
ns
ns
Mb/s
Ω
Ω
USB0_DM
V_CRS
USB0_DP
10% V_OL
t_per - t_jr
90% V_OH
t_r
t_f
Figure 6-48. USB0 Integrated Transceiver Interface Timing
6.24.2 USB0 Unused Signal Configuration
If USB0 is unused, then the USB0 signals should be configured as shown in Section 3.6.19.
Copyright © 2010–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 141
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