AM1705_16 Datasheet, PDF (104/165 Pages) Texas Instruments – AM1705 ARM® Microprocessor

AM1705
SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014
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Table 6-53. Additional⁽¹⁾ SPI0 Master Timings, 5-Pin Option^{(2) (3)}
No.
18 t_{d(SPC_ENA)M}
20 t_{d(SPC_SCS)M}
21 t_{d(SCSL_ENAL)M}
22 t_{d(SCS_SPC)M}
23 t_{d(ENA_SPC)M}
PARAMETER
Max delay for slave to
deassert SPI0_ENA after
final SPI0_CLK edge to
ensure master does not
begin the next transfer.⁽⁴⁾
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Delay from final SPI0_CLK
edge to
master deasserting
SPI0_SCS ^{(5) (6)}
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid after
master asserts SPI0_SCS to delay the
master from beginning the next transfer,
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Delay from SPI0_SCS active
to first SPI0_CLK^{(7) (8) (9)}
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Delay from assertion of
SPI0_ENA low to first
SPI0_CLK edge.⁽¹⁰⁾
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
MIN
0.5t_c(SPC)M + P - 3
P-3
0.5t_c(SPC)M + P - 3
P-3
MAX
UNIT
0.5t_c(SPC)M + P + 5
P+5
ns
0.5t_c(SPC)M + P + 5
P+5
ns
C2TDELAY + P ns
2P - 5
0.5t_c(SPC)M + 2P - 5
ns
2P - 5
0.5t_c(SPC)M + 2P - 5
3P + 3.6
0.5t_c(SPC)M + 3P + 3.6
ns
3P + 3.6
0.5t_c(SPC)M + 3P + 3.6
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
104 Peripheral Information and Electrical Specifications
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