THS1206IDAR Datasheet, PDF (6/43 Pages) Texas Instruments – 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG TO-DIGITAL CONVERTERS

THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE^{(1) (2)}
PARAMETER
tc
Clock cycle of the internal clock oscillator
t1
Pulse width, CONVST
tdA
Aperture time
t2
Time between consecutive start of single con-
version
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 0, TRIG1 = 0
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 0
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 0, TRIG1 = 1
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 1
(1) _{Timing parameters are ensured by design but are not tested.}
(2) _{See Figure 24.}
TEST CONDITIONS
1 analog input
2 analog inputs
3 analog inputs
4 analog inputs
1 analog input
2 analog inputs
3 analog inputs
4 analog inputs
1 analog input, TL = 1
2 analog inputs, TL = 2
3 analog inputs, TL = 3
4 analog inputs, TL = 4
1 analog input, TL = 4
2 analog inputs, TL = 4
3 analog inputs, TL = 6
4 analog inputs, TL = 8
1 analog input, TL = 8
2 analog inputs, TL = 8
3 analog inputs, TL = 9
4 analog inputs, TL = 12
1 analog input, TL = 14
2 analog inputs, TL = 12
3 analog inputs, TL = 12
MIN
151
1.5×tc
2.5×tc
3.5×tc
4.5×tc
2×tc
3×tc
4×tc
5×tc
PIN ASSIGNMENTS
DA PACKAGE
(TOP VIEW)
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TYP
MAX
167
175
UNIT
ns
ns
1
ns
ns
ns
6.5×tc + 15
ns
7.5×tc +15
8.5×tc +15
ns
9.5×tc +15
3×t2 +6.5×tc+15
ns
t2 +7.5×tc+15
t2 +8.5×tc+15
ns
t2 +9.5×tc+15
7×t2 +6.5×tc+15
ns
3×t2 +7.5×tc+15
2×t2 +8.5×tc+15
ns
2×t2 +9.5×tc+15
13×t2 +6.5×tc+15
ns
5×t2 +7.5×tc+15
3×t2 +8.5×tc+15 ns
D0 ₁
D1 ₂
D2 3
D3 4
D4 5
D5 6
BV_DD 7
BGND 8
D6 9
D7 10
D8 11
D9 12
D10/RA0 13
D11/RA1 14
CONV_CLK (CONVST) 15
DATA_AV 16
32 ^AINP
31 ^AINM
30 BINP
29 BINM
28 REFIN
27 REFOUT
26 REFP
25 REFM
24 AGND
23 AV_DD
22 CS0
21 CS1
20 WR (R/W)
19 RD
18 DV_DD
17 DGND
6