THS1206IDAR Datasheet, PDF (16/43 Pages) Texas Instruments – 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG TO-DIGITAL CONVERTERS

THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
DETAILED DESCRIPTION
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Reference Voltage
The THS1206 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and
VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the
reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits
of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS1206 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected individually
and configured as single-ended or differential inputs. The desired analog input channel can be programmed.
Converter
The THS1206 uses a 12-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages, which achieves
a high sample rate with low power consumption. The THS1206 distributes the conversion over several smaller ADC
sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage.
This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A
sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while
the second through the eighth stages operate on the seven preceding samples.
Conversion Modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is
initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion
mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling
edge of the applied clock signal.
DATA_AV
In continuous conversion mode, the first DATA_AV signal is delayed by (7+TL) cycles of CONV_CLK after a FIFO reset
command. This is due to the latency of the pipe line architecture of the THS1206.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows
the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
CHANNEL CONFIGURATION
1 single-ended channel
2 single-ended channels
3 single-ended channels
4 single-ended channels
1 differential channel
2 differential channels
1 single-ended and 1 differential channel
2 single-ended and 1 differential channels
NUMBER OF
CHANNELS
1
2
3
4
1
2
2
3
MAXIMUM CONVERSION
RATE PER CHANNEL
6 MSPS
3 MSPS
2 MSPS
1.5 MSPS
6 MSPS
3 MSPS
3 MSPS
2 MSPS
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
+ fc
6 MSPS
# channels
16