THS1206IDAR Datasheet, PDF (32/43 Pages) Texas Instruments – 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG TO-DIGITAL CONVERTERS

THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
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INTERFACING THE THS1206 TO THE TMS320C54X USING I/O STROBE
The following application circuit shows an interface of the THS1206 to the TMS320C54x. The read and write timings (using
R/W, CS0-controlled) shown before are valid for this specific interface.
DVDD
THS1206
CS0
CS1
RD R/W
DATA_AV
CONV_CLK
DATA
TMS320C54x
I/O STRB
A15
R/W
INTX
BCLK
DATA
Read Timing (using RD, RD-controlled)
Figure 38 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts
as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0,
CS1, and RD, which becomes valid.
CS0
CS1
tsu(CS)
ÓÓÓÓÓÓÓÓÓÓ WR
tw(RD)
RD
10%
D(0–11)
ta
90%
DATA_AV
td(CSDAV)
90%
th(CS) _{ÔÔÔÔÔÔÔÔ}
10%
th
90%
Figure 38. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD-controlled)
PARAMETER
tsu(CS)
ta
td(CSDAV)
th
th(CS)
tw(RD)
Setup time, RD low to last CS valid
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, RD change to first CS invalid
Pulse duration, RD active
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
32