THS1206IDAR Datasheet, PDF (30/43 Pages) Texas Instruments – 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG TO-DIGITAL CONVERTERS

THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
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TIMING AND SIGNAL DESCRIPTION OF THE THS1206
Read Timing (using R/W, CS0-controlled)
Figure 36 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W, which becomes valid.
tw(CS)
CS0
10%
10%
90%
CS1
R/W ^{ÓÓÓÓÓÓÓÓÓ90%}
RD
D(0–11)
DATA_AV
tsu(R/W)
ta
90%
td(CSDAV)
90%
ÔÔÔÔÔÔÔÔÔ ^th(R/W)
90%
th
90%
Figure 36. Read Timing Diagram Using RD (CS0-controlled)
Read Timing Parameter (CS0-controlled)
PARAMETER
tsu(R/W)
ta
td(CSDAV)
th
th(R/W)
tw(CS)
Setup time, R/W high to last CS valid
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, first external CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
30