THS1206IDAR Datasheet, PDF (33/43 Pages) Texas Instruments – 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG TO-DIGITAL CONVERTERS

www.ti.com
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
Write Timing (using WR, WR-controlled)
Figure 39 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input
RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal
of CS0, CS1, and WR, which becomes valid.
CS0
CS1
tsu(CS)
tw(WR)
th(CS)
WR
10%
RD ÓÓÓÓÓÓÓÓ
D(0–11)
90%
10%
tsu ÔÔÔÔÔÔÔÔ
th
90%
DATA_AV ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
Figure 39. Write Timing Diagram Using WR (WR-controlled)
Write Timing Parameter Using WR (WR-controlled)
PARAMETER
tsu(CS)
tsu
th
th(CS)
tw(WR)
Setup time, CS stable to last WR valid
Setup time, data valid to first WR invalid
Hold time, WR invalid to data invalid
Hold time, WR invalid to CS change
Pulse duration, WR active
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
33