THS1206IDAR Datasheet, PDF(28/43 Page) Texas Instruments – 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG TO-DIGITAL CONVERTERS

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THS1206IDAR Datasheet, PDF (28/43 Pages) Texas Instruments – 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG TO-DIGITAL CONVERTERS

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THS1206

SLAS217H â MAY 1999 â REVISED JULY 2003#

www.ti.com

FIFO TRIGGER LEVEL

Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger

level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to

indicate to the processor that the ADC values can be read.

Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be

selected, is dependent on the number of input channels. Both, a differential or a single-ended input is considered as one

channel. The processor therefore always reads the data from the FIFO in the same order and is able to distinguish between

the channels.

BIT 3

TRIG1

BIT 2

TRIG0

Table 13. FIFO Trigger Level

TRIGGER LEVEL

FOR 1 CHANNEL

(ADC values)

TRIGGER LEVEL

FOR 2 CHANNELS

(ADC values)

TRIGGER LEVEL

FOR 3 CHANNEL

(ADC values)

TRIGGER LEVEL

FOR 4 CHANNELS

(ADC values)

Reserved

TIMING AND SIGNAL DESCRIPTION OF THE THS1206

The reading from the THS1206 and writing to the THS1206 is performed by using the chip select inputs (CS0, CS1), the

write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired

in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select inputs

can be used to interface easily to a processor.

Reading from the THS1206 takes place by an internal RDint signal, which is generated from the logical combination of the

external signals CS0, CS1 and RD (see Figure 35). This signal is then used to strobe the words out of the FIFO and to

enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid will make RDint active while

the write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates RDint again.

Writing to the THS1206 takes place by an internal WRint signal, which is generated from the logical combination of the

external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and

1. The last external signal (either CS0, CS1 or WR) to become valid makes WRint active while the read input (RD) is inactive.

The first of those external signals going to its inactive state then deactivates WRint again.

CS0

Read Enable

CS1

Write Enable

Data Bits

Control/Data

Registers

Figure 35. Logical Combination of CS0, CS1, RD, and WR

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