THS1030_13 Datasheet, PDF (6/39 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1030
3ĆV TO 5.5ĆV, 10ĆBIT, 30 MSPS
CMOS ANALOGĆTOĆDIGITAL CONVERTER
SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003
electrical characteristics over recommended operating conditions, AV_DD = 3 V, DV_DD = 3 V, f_s = 30
MSPS/50% duty cycle, MODE = AV_DD, 2-V input span from 0.5 V to 2.5 V, external reference,
T_A = T_min to T_max (unless otherwise noted) (continued)
clock
tc
tw(CKH)
tw(CKL)
td(o)
td(DZ)
td(DEN)
td(AP)
PARAMETER
Clock cycle
Pulse duration, clock high
Pulse duration, clock low
Clock to data valid, delay time
Output disable to Hi-Z output, disable time
Output enable to output valid, enable time
Pipeline latency
Aperture delay time
Aperture uncertainty (jitter)
MIN TYP MAX UNIT
33
ns
15 16.5 110 ns
15 16.5 110 ns
25 ns
20 ns
20 ns
3
Cycles
4
ns
2
ps
power supply (See Note 7)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ICC
Operating supply current
AVDD = DVDD = 3 V, MODE = AVDD
29
40 mA
PD
Power dissipation
AVDD = DVDD = 3 V
AVDD = DVDD = 5 V
87 120
mW
150
PD(STBY) Standby power
AVDD = DVDD = 3 V, MODE = AVDD
3
5 mW
NOTES: 7. Mode and REFSENSE are set to AVDD. The internal reference buffer is powered up to buffer the externally applied 0.5 V REFBS
and 2.5 V REFTS. 1.5 VDC is applied at AIN while converting data at 30 MSPS.
6
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