THS1030_13 Datasheet, PDF (18/39 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1030
3ĆV TO 5.5ĆV, 10ĆBIT, 30 MSPS
CMOS ANALOGĆTOĆDIGITAL CONVERTER
SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003
PRINCIPLES OF OPERATION
top/bottom mode (MODE = AV_DD)
REFTF = AVDD + (REFTS − REFBS)
2
AIN+
REFTS
REFBS
1
−1/2
−1/2
Sample
and
Hold
ADC
Core
Internal
Reference
Buffer
REFBF = AVDD − (REFTS + REFBS)
2
Figure 18. ADC Reference Generation Mode = AV_DD
Connecting MODE to AV_DD enables the internal reference buffer. Its inputs are internally switched to the REFTS
and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections
(REFTS to REFTF) and (REFBS to REFBF) are broken.
The REFTS and REFBS voltages set the analog input span limits FS+ and FS− respectively. Any voltages at
AIN greater than REFTS or less than REFBS will cause ADC over-range, which is signaled by OVR going high
when the conversion result is output.
Typically, REFSENSE is tied to AV_DD to disable the ORG output to VREF (as in Figure 19), but the user can
choose to use the ORG output to VREF as either REFTS or REFBS.
AVDD
+FS
−FS
AIN
MODE
DC SOURCE = FS+
REFTS REFSENSE
DC SOURCE = FS−
0.1 µF
0.1 µF
10 µF 0.1 µF
REFBS
REFTF
REFBF
Figure 19. Top/Bottom Reference Mode
18
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