THS1030_13 Datasheet, PDF(23/39 Page) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

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THS1030_13 Datasheet, PDF (23/39 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

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THS1030

3ÄV TO 5.5ÄV, 10ÄBIT, 30 MSPS

CMOS ANALOGÄTOÄDIGITAL CONVERTER

SLAS243E â NOVEMBER 1999 â REVISED DECEMBER 2003

PRINCIPLES OF OPERATION

power management

In power-sensitive applications (such as battery-powered systems) where the THS1030 ADC is not required

to convert continuously, power can be saved between conversion intervals by placing the THS1030 into

power-down mode. This is achieved by setting pin 17 (STBY) to 1. In power-down mode, the device typically

consumes less than 1 mW of power (from AVDD and DVDD) in either top/bottom mode or center-span mode.

On power up, the THS1030 typically requires 5 ms of wake-up time before valid conversion results are available

in either top/bottom or center span modes.

Disabling the ORG in applications where the ORG output is not required can also reduce power dissipation by

1 mA analog IDD. This is achieved by connecting the REFSENSE pin to AVDD.

output format and digital I/O

While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input

over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.

The ADC output data format is unsigned binary (output codes 0 to 1023).

driving the THS1030 analog inputs

driving AIN

Figure 26 shows an equivalent circuit for the THS1030 AIN pin. The load presented to the system at the AIN

pin comprises the switched input sampling capacitor, CSAMPLE, and various stray capacitances, CP1 and CP2.

AVDD

CLK

1.2 pF

AIN

8 pF

C2 C(Sample)

1.2 pF

AGND

CLK

_ VLAST

Figure 27. Equivalent Circuit of Analog Input AIN

In any single-ended input mode, VLAST = the average of the previously sampled voltage at AIN and the average

of the voltages on pins REFTS and REFBS. In any differential mode, VLAST = the common mode input voltage.

The external source driving AIN must be able to charge and settle into CSAMPLE and the CP1 and CP2 strays

to within 0.5 LSB error while sampling (CLK pin low) to achieve full ADC resolution.

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