THS1030_13 Datasheet, PDF (4/39 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1030
3ĆV TO 5.5ĆV, 10ĆBIT, 30 MSPS
CMOS ANALOGĆTOĆDIGITAL CONVERTER
SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003
recommended operating conditions (continued)
sampling rate and resolution
fs
Sample frequency
Resolution
PARAMETER
MIN NOM MAX UNIT
5
30 MSPS
10
Bits
electrical characteristics over recommended operating conditions, AV_DD = 3 V, DV_DD = 3 V, f_s = 30
MSPS/50% duty cycle, MODE = AV_DD, 2-V input span from 0.5 V to 2.5 V, external reference,
T_A = T_min to T_max (unless otherwise noted)
analog inputs
PARAMETER
VI(AIN)
CI
BW
Analog input voltage
Switched sampling input capacitance
Full power bandwidth (−3 dB)
Ilkg
DC leakage current (input = ± FS)
VREF reference voltages
PARAMETER
Internal 1-V reference voltage (REFSENSE = VREF)
Internal 2-V reference voltage (REFSENSE = AGND)
External reference voltage (REFSENSE = AVDD)
Reference input resistance
MIN
REFBS
TYP MAX
REFTS
1.2
150
60
UNIT
V
pF
MHz
µA
MIN TYP MAX UNIT
0.95
1 1.05 V
1.90
2 2.10 V
1
2V
680
Ω
REFTF, REFBF reference voltages
PARAMETER
TEST CONDITIONS
MIN TYP MAX
Differential input voltage (REFTF − REFBF) (REFSENSE = VREF)
0.9
1 1.1
Differential input voltage (REFTF − REFBF) (REFSENSE = AGND)
1.9
2 2.1
Input common mode voltage (REFTF + REFBF)/2
REFTF voltage (MODE = AVDD)
VREF = 1 V
VREF = 2 V
REFBF voltage (MODE = AVDD)
Input resistance between REFTF and REFBF
VREF = 1 V
VREF = 2 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
1.3 1.5 1.7
2 2.5
3
2
3
2.5
3.5
1
2
0.5
1.5
600
Power up time for valid ADC conversions (tPUconv)
See Note 1
1.2
NOTES: 1. Time from control register STBY pin returning low to the ADC conversion to be accurate within 0.1% of fullscale.
UNIT
V
V
V
V
V
V
V
Ω
µs
4
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