THS1030_13 Datasheet, PDF (25/39 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1030
3ĆV TO 5.5ĆV, 10ĆBIT, 30 MSPS
CMOS ANALOGĆTOĆDIGITAL CONVERTER
SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003
PRINCIPLES OF OPERATION
equivalent input resistance at AIN and ac-coupling to AIN
Some applications may require ac-coupling of the input signal to the AIN pin. Such applications can use an
ac-coupling network such as shown in Figure 29.
AVDD
R(Bias1)
Cin
AIN
R(Bias2)
Figure 29. AC-Coupling the Input Signal to the AIN Pin
Note that if the bias voltage is derived from the supplies, as shown in Figure 29, then additional filtering should
be used to ensure that noise from the supplies does not reach AIN.
Working with the input current pulse equations given in the previous section is awkward when designing
ac-coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent
resistance, R_AIN, from the AIN pin to a voltage source VM where
VM = (REFTS + REFBS)/2 and R_AIN = 1 / (C_S x f_clk)
where f_clk is the CLK frequency.
The high-pass −3 dB cutoff frequency for the circuit shown in Figure 29 is:
ǒ Ǔ ^{f(*3 dB) +} ₂
1
p RINtot
(10)
where R_INtot is the parallel combination of Rbias1, Rbias2, and R_AIN. This approximation is good provided that
the clock frequency, f_clk, is much higher than f(−3 dB).
Note also that the effect of the equivalent R_AIN and VM at the AIN pin must be allowed for when designing the
bias network dc level.
details
The above value for R_AIN is derived by noting that the average AIN voltage must equal the bias voltage supplied
by the ac coupling network. The average value of V_LAST in equation 8 is thus a constant voltage
V_LAST = V(AIN bias) – VM
For an input voltage Vin at the AIN pin,
Qin = (Vin – V_LAST) x Cs
Provided that f (−3 dB) is much lower than f_clk, a constant current flowing over the clock period can approximate
the input charging pulse
Iin = Qin / t_clk
= Qin x f_clk
= (Vin – V_LAST) x C_S x f_clk
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