THS1030_13 Datasheet, PDF (21/39 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1030
3ĆV TO 5.5ĆV, 10ĆBIT, 30 MSPS
CMOS ANALOGĆTOĆDIGITAL CONVERTER
SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
VBG
+
_
Internal
Reference
Buffer
Mode =
AVDD
+
2
VREF = External
_
REFSENSE
AVDD
AGND
Figure 23. Drive VREF Mode
operating configuration examples
This section provides examples of operating configurations.
Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF
to drive REFTS. Connecting the mode pin to AV_DD puts the THS1030 in top/bottom mode. Connecting pin
REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are user-connected to VREF and
AGND respectively to match the AIN pin input range to the voltage range of the input signal.
AVDD
2V
1V
0V
AIN
MODE
VREF = 2 V
0.1 µF
0.1 µF
REFTS
10 µF
REFTF
REFSENSE
0.1 µF
REFBF
REFBS
Figure 24. Operation Configuration in Top/Bottom Mode
In Figure 25 the input signal is differential, so mode = AV_DD/2 (differential mode) is set to allow the inverse signal
to be applied to REFTS and REFBS. The differential input goes from −0.8 V to 0.8 V, giving a total input signal
span of 1.6 V, REFTF−REFBF should therefore equal 1.6 V. REFSENSE is connected to resistors RA and RB
(external divider mode) to make VREF = 1.6 V, that is R_A/R_B = 0.6 (see Figure 22).
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