THS1030_13 Datasheet, PDF (29/39 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1030
3ĆV TO 5.5ĆV, 10ĆBIT, 30 MSPS
CMOS ANALOGĆTOĆDIGITAL CONVERTER
SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003
PRINCIPLES OF OPERATION
user tips for obtaining best performance from the THS1030
D Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails.
D ORG modes offer the simplest configurations for ADC reference generation.
D Choose differential input mode for best distortion performance.
D Choose a 2-V ADC input span for best noise performance.
D Choose a 1-V ADC input span for best distortion performance.
D If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the
system. Care should be taken to ensure noise is not injected into the THS1030.
D Use external voltage sources for ADC reference generation where there are stringent requirements on
accuracy and drift.
D Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB
traces.
TLC876 mode
The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher
speed by dropping the THS1030 into their sockets. Grounding the 1876M pin effectively puts the THS1030 into
876 mode using the external ADC reference. The MODE pin should either be grounded or left floating.
The REFSENSE pin is connected to DV_DD when the THS1030 is dropped into a TLC876 socket. For
DV_DD = 5-V applications, this will disable the ORG. For TLC876 applications using DV_DD = 3.3 V, the VREF pin
will be driven to AV_SS. In TLC876/AD876 mode, the pipeline latency is increased to 3.5 clock cycles to match
the TLC876 latency.
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