SMJ320C26B Datasheet, PDF (6/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
16 × 16 bit parallel multiplier (continued)
Incorporated into the SMJ320C26 instruction set are single-cycle multiply/accumulate instructions that allow
both operands to be fetched simultaneously. The data for these operations may reside anywhere in internal or
external memory, and can be transferred to the multiplier each cycle via the program and data buses.
Four product shift modes are available at the Product Register (PR) output that are useful when performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
timer
The SMJ320C26 provides a memory mapped 16-bit timer for control operations. The on-chip timer (TIM)
register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every
time the timer decrements to zero, provided the timer interrupt is enabled. The timer is reloaded with the value
contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts may be
programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT1.
memory control
The SMJ320C26 provides a total of 1568 words of 16 bit on-chip RAM, divided into four separate blocks (B0,
B1, B2, and B3). Of the 1568 words, 32 words (block B2) are always data memory, and all other blocks are
programmable as either data or program memory. A data memory size of 1568 words allows the SMJ320C26
to handle a data array of 1536 words, while still leaving 32 locations for intermediate storage. When using B0,
B1, or B3 as program memory, instructions can be downloaded from external memory into on-chip RAM, and
then executed.
When using on-chip program RAM, ROM, or high speed external program memory, the SMJ320C26 runs at
full speed without wait states. However, the READY line can be used to interface the SMJ320C26 to slower,
less expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM
speeds processing and cuts overall system costs.
The SMJ320C26 provides three separate address spaces for program memory, data memory, and I/O. The
on-chip memory is mapped into either the data memory or program memory space, depending upon the choice
of memory configuration.
The instruction configuration (parameter) is used as follows to configure the blocks B0, B1, and B3 as program
or as data memory.
CONFIGURATION
0
1
2
3
B0
Data
Program
Program
Program
B1
Data
Data
Program
Program
B3
Data
Data
Data
Program
Regardless of the configuration, the user may still execute from external program memory.
The SMJ320C26 provides a ROM of 256 words. The ROM is sufficient to allow the programming of a bootstrap
program and interrupt handler, or to implement self test routines.
The SMJ320C26 has six registers that are mapped into the data memory space at the locations 0–5; a serial
port data receive register, serial port data transmit register, timer register, period register, interrupt mask register,
and global memory allocation register.
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