SMJ320C26B Datasheet, PDF (26/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
SERIAL PORT TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
MIN
td(CH-DX)
td(FL-DX)
td(CH-FS)
DX valid after CLKX rising edge (see Note 8)
DX valid after FSX falling edge (TXM = 0) (see Note 8)
FSX valid after CLKX rising edge (TXM = 1)
MAX
80
45
45
UNIT
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
MIN
MAX UNIT
fsx
Serial port frequency
1.25
5,000 kHz
tc(SCK) Serial port clock (CLKX/CLKR) cycle time
200 800,000 ns
tw(SCK) Serial port clock (CLKX/CLKR) low pulse duration (see Note 9)
80
ns
tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 9)
80
ns
tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)
18
ns
th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)
20
ns
tsu(DR) DR setup time before CLKR falling edge
10
ns
th(DR) DR hold time after CLKR falling edge
20
ns
NOTES: 1. Q = 1/4tc(C)
8. The last occurrence of FSX falling and CLKX rising.
9. The duty cycle of the serial port clock must be within 40–60%. Serial port clock (CLKX/CLKR) rise and fall times must be less than
25 ns.
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