SMJ320C26B Datasheet, PDF (12/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
addressing modes
The SMJ320C26 instruction set provides three memory addressing modes; direct, indirect, and immediate
addressing.
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the
instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data
memory address. Indirect addressing accesses data memory through the eight auxiliary registers. In immediate
addressing, the data is embedded in the instruction word(s).
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus, memory
is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.
Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific
auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0 through
AR7 respectively.
There are seven types of indirect addressing: auto increment, auto decrement, post indexing by either adding
or subtracting the contents of AR0, single indirect addressing with no increment or decrement and bit reversal
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, followed by an ARP update.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table
read/writes, allows a single instruction to be executed up to 256 times. The repeat counter (RPTC) is loaded
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this
operand is one less than the number of times that the next instruction is executed. Those instructions that are
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle
instructions.
instruction set
The SMJ320C26 microprocessor implements a comprehensive instruction set that supports both numeric
intensive signal processing operations as well as general purpose applications, such as multiprocessing and
high speed control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the
same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary
depending upon whether the next data operand fetch is from internal or external program memory. Highest
throughput is achieved by maintaining data memory on-chip and using either internal or fast program memory.
Table 1 lists the symbols and abbreviations used in Table 2, the instruction set summary. Table 2 consists
primarily of single-cycle, single-word instructions. Infrequently used branch, I-O, and CALL instructions are
multicycle. The instruction set summary is arranged according to function and alphabetized within each
functional grouping. The symbol (^‡) indicates instructions that are not included in the SMJ320C25 instruction
set.
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