SMJ320C26B Datasheet, PDF (25/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
HOLD TIMING
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
td(C1L-AL) HOLDA low after CLKOUT1 low
tdis(AL-A) HOLDA low to address three-state
tdis(C1L-A) Address three-state after CLKOUT1 low (HOLD mode) (see Note 7)
td(HH-AH) HOLD high to HOLDA high
ten(A-C1L) Address driven before CLKOUT1 low (HOLD mode) (see Note 7)
† _{This parameter is not production tested.}
MIN TYP
–1^†
0
MAX
10
20^†
25
8^†
UNIT
ns
ns
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
td(C2H-H) HOLD valid after CLKOUT2 high
NOTES: 1. Q = 1/4tc(C)
7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”
MIN MAX UNIT
Q–24 ns
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