SMJ320C26B Datasheet, PDF (11/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
interrupts and subroutines
The SMJ320C26 has three external maskable user interrupts INT2–INT0, available for external devices that
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),
and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest
priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on
two-words boundaries so that branch instructions can be accommodated in those locations if desired.
A built in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction is completed. This mechanism applies both to
instructions that are repeated or become multicycle due to the READY signal.
external interface
The SMJ320C26 supports a wide range of system interfacing requirements. Program, data, and I/O address
spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by
having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the
processor’s external address and data busses in the same manner as memory-mapped devices. Interface to
memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are
made with slower devices, the SMJ320C26 processor waits until the other device completes its function and
signals the processor via the READY line, the SMJ320C26 then continues execution.
A serial port provides communication with serial devices, such as codecs, serial A/D converters, and other serial
systems. The interface signals are compatible with codecs and many other serial devices with a minimum of
external hardware. The serial port may also be used for intercommunication between processors in
multiprocessing applications.
The serial port has two memory mapped registers; the data transmit register (DXR) and the data receive register
(DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same
manner as any other data memory location. Each register has an external clock, a framing signal, and
associated shift registers. One method of multiprocessing may be implemented by programming one device
to transmit while the others are in the receive mode.
multiprocessing
The flexibility of the SMJ320C26 allows configurations to satisfy a wide range of system requirements. The
SMJ320C26 can be used as follows:
D A standalone processor.
D A multiprocessor with devices in parallel.
D A multiprocessor with global memory space.
D A peripheral processor interfaced via processor controlled signals to another device.
For multiprocessing applications, the SMJ320C26 has the capability of allocating global data memory space
and communicating with that space via the BR (bus request) and READY control signals. Global memory is data
memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit memory
mapped GREG (global memory allocation register) specifies part of the SMJ320C26’s data memory as global
external memory. The contents of the register determine the size of the global memory space. If the current
instruction addresses a location within that space, BR is asserted to request control of the data bus. The length
of the memory cycle is controlled by the READY line.
The SMJ320C26 supports DMA (direct memory access) to its external program/data memory using the HOLD
and HOLDA signals. Another processor can take complete control of the SMJ320C26’s external memory by
asserting HOLD low. This causes the SMJ320C26 to place its address, data, and control lines in a high
impedance state, and assert HOLDA.
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