SMJ320C26B Datasheet, PDF (3/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PIN NOMENCLATURE
NAME
VCC
VSS
X1
X2/CLKIN
CLKOUT1
CLKOUT2
D15–D0
A15–A0
PS, DS, IS
R/W
STRB
RS
INT2, INT1, INT0
MP/MC
MSC
IACK
READY
I/O/Z^†
I
I
O
I
O
O
I/O/Z
O/Z
O/Z
O/Z
O/Z
I
I
I
O
O
I
DEFINITION
5-V supply pins.
Ground pins.
Output from internal oscillator for crystal.
Input to internal oscillator from crystal or external clock.
Master clock output (crystal or CLKIN frequency/4).
A second clock output signal.
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data and I/O spaces.
16-bit address bus A15 (MSB) through A0 (LSB).
Program, data and I/O space select signals.
Read/write signal.
Strobe signal.
Reset input.
External user interrupt inputs.
Microprocessor/microcomputer mode select pin.
Microstate complete signal.
Interrupt acknowledge signal.
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction
is complete.
BR
XF
HOLD
O Bus request signal. Asserted when the SMJ320C26 requires access to an external global data memory space.
O External flag output (latched software – programmable signal).
Hold input. When asserted, SMJ320C26 goes into an idle mode and places the data address and control lines
I
in the high-impedance state.
HOLDA
O Hold acknowledge signal.
SYNC
I
Synchronization input.
BIO
I
Branch control input. Polled by BIOZ instruction.
DR
I
Serial data receive input.
CLKR
I
Clock input for serial port receiver.
FSR
I
Frame synchronization pulse for receive input.
DX
O/Z Serial data transmit output.
CLKX
I
Clock input for serial port transmitter.
FSX
I/O/Z Frame synchronization pulse for transmit. May be configured as either an input or an output.
† _{I/O/Z denotes input/output/high-impedance state.}
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