SMJ320C26B Datasheet, PDF (34/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
CLKOUT1
CLKOUT2
STRB
HOLD
PS, DS,
OR IS
R/W
ten(A-C1L)
td(C2H-H) (see note A)
VALID
D15–D0
IN
td(HH-AH)
HOLDA
A15–A0
N+2
N+2
FETCH
–
–
–
N+2
EXECUTE
–
–
–
N+1
NOTE A: HOLD is an asynchronous input that can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown
will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
Figure 13. HOLD Timing (Part B)
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