SMJ320C26B Datasheet, PDF (23/40 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
td(C1-S) STRB from CLKOUT1 (if STRB is present)
td(C2-S) CLKOUT2 to STRB (if STRB is present)
tsu(A)
Address setup time before STRB low (see Note 3)
th(A)
Address hold time after STRB high (see Note 3)
tw(SL) STRB low pulse duration (no wait states, see Note 4)
tw(SH) STRB high pulse duration (between consecutive cycles, see Note 4)
tsu(D)W Data write setup time before STRB high (no wait states)
th(D)W Data write hold time from STRB high
ten(D) Data bus starts being driven after STRB low (write cycle)
tdis(D) Data bus three-state after STRB high (write cycle)
td(MSC) MSC valid from CLKOUT1
† _{This parameter is not production tested.}
MIN TYP
Q–6
Q
–6
0
Q–12
Q–8
2Q–5 2Q
2Q
2Q–20
Q–10
Q
0^†
Q
– 10^†
0
MAX
Q+6
6
2Q+5
Q+15^†
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
ta(A)
Read data access time from address time (read cycle) (see Notes 3 and 5)
tsu(D)R Data read setup time before STRB high
th(D)R
Data read hold time from STRB high
td(SL-R) READY valid after STRB low (no wait states)
td(C2H-R) READY valid after CLKOUT2 high
th(SL-R) READY hold time after STRB low (no wait states)
th(C2H-R) READY hold after CLKOUT2 high
td(M-R) READY valid after MSC valid
th(M-R) READY hold time after MSC valid
† _{This parameter is not production tested.}
MIN
MAX
3Q–40
23
0
Q–22
Q – 22^†
Q+3
Q + 3^†
0^†
2Q –25^†
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS, INT, BIO, AND XF TIMING
switching characteristics over recommended operating conditions (see Note 1)
td(RS)
td(IACK)
td(XF)
PARAMETER
CLKOUT1 low to reset state entered
CLKOUT1 to IACK valid
XF valid before falling edge of STRB
MIN
– 8^†
Q–12
TYP MAX UNIT
22^† ns
0
8 ns
ns
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