BQ24157S Datasheet, PDF (6/45 Pages) Texas Instruments – Full USB Compliance and USB-OTG Support

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bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
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Electrical Characteristics (continued)
Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), T_J = –40°C to 125°C, T_J = 25°C for typical
values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
INPUT CURRENT LIMITING
I_{IN_LIMIT}
Input current limiting threshold
VREF BIAS REGULATOR
I_IN = 100 mA
I_IN = 500 mA
T_J = 0°C to 125°C
T_J = –40°C to 125°C
T_J = 0°C to 125°C
T_J = –40°C to 125°C
88
93
98
mA
86
93
98
450
475
500
mA
440
475
500
V_REF
Internal bias regulator voltage
V_REF output short current limit
BATTERY RECHARGE THRESHOLD
VBUS > V_IN(min) or V_(CSOUT) > VBUS(min),
I_(VREF) = 1 mA, C_(VREF) = 1 μF
2
6.5
V
30
mA
V_(RCH)
Recharge threshold voltage
Deglitch time
STAT OUTPUTS
Below V_(OREG)
V_(SCOUT) decreasing below threshold,
t_FALL = 100 ns, 10-mV overdrive
100
120
150 mV
130
ms
V_OL(STAT)
Low-level output saturation voltage, STAT pin
High-level leakage current for STAT
I_O = 10 mA, sink current
Voltage on STAT pin is 5 V
0.55
V
1 μA
I²C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
V_OL
Output low threshold level
V_IL
Input low threshold level
V_IH
Input high threshold level
I_(BIAS)
Input bias current
f_(SCL)
SCL clock frequency
BATTERY DETECTION
I_O = 10 mA, sink current
V_(pullup) = 1.8 V, SDA and SCL
V_(pullup) = 1.8 V, SDA and SCL
V_(pullup) = 1.8 V, SDA and SCL
0.4
V
0.4
V
1.2
V
1 μA
3.4 MHz
I_(DETECT)
Battery detection current before charge done
(sink current) ⁽²⁾
t_DETECT
Battery detection time
SLEEP COMPARATOR
Begins after termination detected,
V_(CSOUT) ≤ V_(OREG)
–0.5
mA
262
ms
V_(SLP)
Sleep-mode entry threshold,
VBUS – V_CSOUT
V_{(SLP_EXIT)}
Sleep-mode exit hysteresis
Deglitch time for VBUS rising above V_(SLP) +
V_{(SLP_EXIT)}
UNDERVOLTAGE LOCKOUT (UVLO)
2.3 V ≤ V_(CSOUT) ≤ V_(OREG), V_BUS falling
2.3 V ≤ V_(CSOUT) ≤ V_(OREG)
Rising voltage, 2-mV overdrive, t_RISE = 100 ns
0
40
100 mV
140
200
260 mV
30
ms
UVLO
UVLO_(HYS)
IC active threshold voltage
IC active hysteresis
Power up delay
V_BUS rising – exits UVLO
V_BUS falling below UVLO – enters UVLO
3.05
3.3 3.55
V
120
150
mV
140
ms
PWM
Voltage from BOOT pin to SW pin
During charge or boost operation
6.5
V
Internal top reverse blocking MOSFET on-
resistance
I_IN(LIMIT) = 500 mA, measured from VBUS to PMID
180
250
Internal top N-channel switching MOSFET on-
resistance
Internal bottom N-channel MOSFET on-
resistance
Measured from PMID to SW,
V_BOOT – V_SW= 4 V
Measured from SW to PGND
120
250 mΩ
110
210
f_(OSC)
Oscillator frequency
Frequency accuracy
–10%
3.0
MHz
10%
D_(MAX)
Maximum duty cycle
99.5%
D_(MIN)
Minimum duty cycle
0
Synchronous mode to non-synchronous mode
transition current threshold⁽²⁾
Low-side MOSFET cycle-by-cycle current sensing
100
mA
(2) Bottom N-channel FET always turns on for approximately 30 ns, and then turns off if current is too low.
6
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