BQ24157S Datasheet, PDF (36/45 Pages) Texas Instruments – Full USB Compliance and USB-OTG Support

Not Recommended for New Designs
bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
11 Layout
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11.1 Layout Guidelines
Give special attention to the PCB layout. The following list provides guidelines:
• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor
connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area
from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation
problems, proper layout to minimize high frequency current path loop is critical (see Figure 37). The sense
resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads
connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other
on adjacent layers (do not route the sense leads through a high-current path, see Figure 38).
• Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components
such that routing interrupts power stage currents). All small control signals should be routed away from the
high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, and one via per capacitor for
small-signal components). A star ground design approach is typically used to keep circuit block currents
isolated (high-power/low-power small-signal), which reduces noise-coupling and ground-bounce issues. A
single ground plane for this design gives good results. With this small layout and a single ground plane, there
is no ground-bounce issue, and having the components segregated minimizes coupling between signals.
• The high-current charge paths into VBUS, PMID, and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• Place 4.7-μF input capacitor as close to PMID pin and PGND pin as possible to make the high frequency
current loop area as small as possible. Place 1-μF input capacitor as close to VBUS pin and PGND pin as
possible to make high frequency current loop area as small as possible (see Figure 39).
11.2 Layout Example
VBUS
L1
R1
SW
V _BAT
VIN
C1
PMID
C2
High
Frequency
Current
Path
PGND
BAT
C3
Figure 37. High Frequency Current Path
36
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