BQ24157S Datasheet, PDF (23/45 Pages) Texas Instruments – Full USB Compliance and USB-OTG Support

Not Recommended for New Designs
www.ti.com
Recognize START or
REPEATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
Recognize STOP or
REPEATED START
Condition
P
Sr
R/W
SCL
S
or
Sr
ACK
Clock Line Held Low While
Interrupts are Serviced
Figure 25. Bus Protocol
Sr
ACK
or
P
8.3.16.2 HS Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a START condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated START condition (a repeated START condition has the same timing as
the start condition). After this repeated START condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a STOP condition, repeated
START conditions should be used to secure the bus in HS-mode. If a transaction is terminated prematurely, the
master needs to send a STOP condition to prevent the slave I²C logic from getting stuck in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
8.3.16.3 I²C Update Sequence
The IC requires a start condition, a valid I²C address, a register address byte, and a data byte for a single
update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of
a single clock pulse. A valid I²C address selects the IC. The IC performs an update on the falling edge of the
acknowledge signal that follows the LSB byte.
For the first update, the IC requires a START condition, a valid I²C address, a register address byte, and a data
byte. For all consecutive updates, the IC needs a register address byte and a data byte. When a STOP condition
is received, the IC releases the I²C bus and awaits new start conditions.
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: bq24157S
Submit Documentation Feedback
23