BQ24157S Datasheet, PDF (3/45 Pages) Texas Instruments – Full USB Compliance and USB-OTG Support

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Not Recommended for New Designs
bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
5 Description (continued)
Charge is terminated based on battery voltage and user-selectable minimum current level. During normal
operation, the IC automatically restarts the charge cycle if the battery voltage falls below an internal threshold
and automatically enters sleep mode or high impedance mode when the input supply is removed. The charge
status can be reported to the host using the I²C interface. During the charging process, the IC monitors its
junction temperature (T_J) and reduces the charge current after T_J increases to about 125°C. To support a USB
OTG device, bq24157S can provide VBUS (5.05 V) by boosting the battery voltage. The IC is available in 20-pin
DSBGA package.
6 Pin Configuration and Functions
20-Bump DSBGA Package
(Top View)
A1
A2
A3
A4
VBUS
VBUS
BOOT
SCL
B1
PMID
B2
PMID
C1
C2
SW
SW
B3
PMID
C3
SW
B4
SDA
C4
STAT
D1
PGND
E1
CSIN
D2
PGND
E2
CD
D3
PGND
D4
OTG
E3
VREF
E4
CSOUT
PIN
NAME
NUMBER
BOOT
A3
CD
E2
CSIN
E1
CSOUT
E4
OTG
D4
PGND
PMID
SCL
SDA
STAT
SW
VBUS
VREF
D1, D2, D3
B1, B2, B3
A4
B4
C4
C1, C2, C3
A1, A2
E3
Pin Functions
I/O
DESCRIPTION
I/O
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 33-nF ceramic capacitor (voltage rating ≥10 V)
from BOOT pin to SW pin.
I Charge disable control pin. CD = 0, charge is enabled. CD = 1, charge is disabled and VBUS pin is high impedance to GND.
I
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic capacitor to PGND
is required.
I
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are long
inductive leads to battery.
Boost mode enable control or input current limiting selection pin. When OTG is in active status, the device is forced to
I
operate in boost mode. It has higher priority over I²C control and can be disabled using the control register. At POR while in
DEFAULT mode, the OTG pin is the default to be used as the input current limiting selection pin. The I²C register is ignored
at startup. When OTG = High, I_{IN_LIMIT} = 500 mA and when OTG = Low, I_{IN_LIMIT} = 100 mA.
Power ground
I/O
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-μF capacitor
from PMID to PGND.
I I²C interface clock. Connect a 10-kΩ pullup resistor to 1.8-V rail (V_AUX= V_{CC_HOST})
I/O I²C interface data. Connect a 10-kΩ pullup resistor to 1.8-V rail (V_AUX= V_{CC_HOST})
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs pulse is sent
O out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or communicate with
a host processor.
O Internal switch to output inductor connection
I/O
Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to the load during
boost mode.
O
Internal bias regulator voltage. Connect a 1-µF ceramic capacitor from this output to PGND. TI does not recommend an
external load on VREF.
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