BQ24157S Datasheet, PDF (21/45 Pages) Texas Instruments – Full USB Compliance and USB-OTG Support

Not Recommended for New Designs
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bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
8.3.15 High Impedance (Hi-Z) Mode
In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the
CD pin high causes the charger to enter Hi-Z mode. When in DEFAULT mode and the CD pin is low, the charger
automatically enters Hi-Z mode if either:
• VBUS > UVLO and a battery with V_BAT > V_LOWV is inserted, or
• VBUS falls below UVLO.
When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is
set to 1 and OTG pin is not in active status.
To exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO, and the HOST must write a 0 to
the HZ-MODE control bit.
8.3.16 Serial Interface Description
I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
The IC works as a slave and is compatible with the following data transfer modes, as defined in the I²C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write
mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.2 V (typical). I²C is asynchronous, which means that it runs off of SCL. The
device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, TI recommends that
SDA changes while SCL is low.
The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode
in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-
mode. The bq24157S device supports 7-bit addressing only. The device 7-bit address is defined as 1101010
(6AH).
8.3.16.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 22. All I²C-compatible devices should
recognize a start condition.
DATA
CLK
S
START Condition
Figure 22. Start and Stop Condition
P
STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the Read or Write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 23). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device
with a matching address generates an acknowledge (see Figure 23) by pulling the SDA line low during the entire
high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link
with a slave has been established.
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