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BQ24157S Datasheet, PDF (22/45 Pages) Texas Instruments – Full USB Compliance and USB-OTG Support
Not Recommended for New Designs
bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
DATA
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CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 23. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 25). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not
listed in this section will result in FFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
START
Condition
Not Acknowledge
Acknowledge
1
2
8
Figure 24. Acknowledge on the I2C Bus
9
Clock Pulse for
Acknowledgement
22
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