BQ24157S Datasheet, PDF (18/45 Pages) Texas Instruments – Full USB Compliance and USB-OTG Support

Not Recommended for New Designs
bq24157S
SLUSB76B – FEBRUARY 2013 – REVISED MAY 2015
www.ti.com
Feature Description (continued)
8.3.8 PWM Controller in Charge Mode
The IC provides an integrated, fixed 3-MHz frequency voltage-mode controller to regulate charge current or
voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation
network used for both continuous and discontinuous current conduction operation. The voltage and current loops
are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable
operation, allowing the use of small ceramic capacitors with a low ESR. The device operates between 0% to
99.5% duty cycles.
The IC has back-to-back common-drain N-channel FETs at the high side and one N-channel FET at the low side.
The input N-FET (Q1) prevents battery discharge when VBUS is lower than V_CSOUT. The second high-side N-FET
(Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap
circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2.
Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4-
A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM controller will operate in
synchronous or non-synchronous mode. This threshold is set to 100 mA and it turns off the low-side N-channel
FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used
when the current of the low-side FET is greater than 100 mA to minimize power losses.
8.3.9 Battery Charging Process
At the beginning of precharge, while battery voltage is below the V_(SHORT) threshold, the IC applies a short-circuit
current, I_(SHORT), to the battery. When the battery voltage is above V_SHORT and below V_OREG, the charge current
ramps up to fast charge current, I_OCHARGE, or a charge current that corresponds to the input current of I_{IN_LIMIT}.
The slew rate for fast charge current is controlled to minimize the current and voltage overshoot during transient.
Both the input current limit, I_{IN_LIMIT}, and fast charge current, I_OCHARGE, can be set by the host. When the battery
voltage reaches the regulation voltage, V_OREG, the charge current is tapered down, as shown in Figure 27. The
voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins.
In HOST mode, the regulation voltage is adjustable (3.5 to 4.44 V) and is programmed through I²C interface. In
DEFAULT mode, the regulation voltage is fixed at 3.54 V.
The IC monitors the charging current during the voltage regulation phase. If termination is enabled, during the
normal charging process with HOST control, after the voltage at the CSOUT pin is above the battery recharge
threshold, V_OREG – V_RCH for the 32-ms (typical) deglitch period, and the termination charge current I_TERM is
detected, the IC turns off the PWM charge and enables a discharge current, I_DETECT, for a period of t_DETECT (262-
ms typical), then checks the battery voltage. If the battery voltage is still above the recharge threshold after
t_DETECT, the battery charging is complete. The battery detection routine is used to ensure termination did not
occur because the battery was removed. After 40 ms (typical) for synchronization purposes of the EOC state and
the counter, the status bit and pin are updated to indicate charging has completed. The termination current level
is programmable. To disable the charge current termination, the host can set the charge termination bit (TE) of
charge control register to 0, refer to I²C Update Sequence for details.
A new charge cycle is initiated when one of the following conditions is detected:
• The battery voltage falls below the V_(OREG) – V_(RCH) threshold.
• VBUS POR, if battery voltage is below the V_(LOWV) threshold.
• CE bit toggle or RESET bit is set (host controlled)
8.3.10 Thermal Regulation and Protection
To prevent overheating of the chip during the charging process, the IC monitors the junction temperature, T_J, of
the die and begins to taper down the charge current after T_J reaches the thermal regulation threshold, T_CF. The
charge current is reduced to 0 when the junction temperature increases approximately 10°C above T_CF. In any
state, if T_J exceeds T_SHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and all
timers are frozen. Charging resumes when T_J falls below T_SHTDWN by approximately 10°C.
18
Submit Documentation Feedback
Product Folder Links: bq24157S
Copyright © 2013–2015, Texas Instruments Incorporated