DS80PCI810 Datasheet, PDF (51/60 Pages) Texas Instruments – Low-Power 8 Gbps 8-Channel Linear Repeater

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10 Layout
DS80PCI810
SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
10.1 Layout Guidelines
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 100 Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used
sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias
are used, the layout must also provide for a low inductance path for the return currents as well. Route the
differential signals away from other signals and noise sources on the printed circuit board. To minimize the
effects of crosstalk, a 5:1 ratio or greater should be maintained between inter-pair and intra-pair spacing. See
AN-1187 “Leadless Leadframe Package (LLP) Application Report” (literature number SNOA401) for additional
information on QFN (WQFN) packages.
10.2 Layout Example
Figure 32 depicts different transmission line topologies which can be used in various combinations to achieve the
optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by
increasing the swell around each hole and by providing for a low inductance return current path. When the via
structure is associated with a thick backplane PCB, further optimization such as back drilling is often used to
reduce the detrimental high frequency effects of stubs on the signal path.
EXTERNAL MICROSTRIP
100 mils
20 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
VDD
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ¹
19
54
20
53
21
52
22
51
23
BOTTOM OF PKG
50
GND
24
49
25
48
26
47
27
46
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD
VDD
Figure 32. Typical Routing Options
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