DS80PCI810 Datasheet, PDF (5/60 Pages) Texas Instruments – Low-Power 8 Gbps 8-Channel Linear Repeater

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DS80PCI810
SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
Pin Functions⁽¹⁾ (continued)
PIN NAME
PIN NUMBER
ENSMB = Float (SMBus MASTER MODE)
SCL
50
SDA
49
AD0-AD3
READ_EN
54, 53, 47, 46
26
RESERVED2
21
RESERVED3
19
ENSMB = 0 (PIN MODE)
EQA
20
EQB
46
VODB0
53
VODB1
54
VODA0
49
VODA1
50
AD2
47
SD_TH
26
RESERVED2
21
I/O, TYPE
DESCRIPTION
I, LVCMOS,
O, OPEN Drain
I, LVCMOS,
O, OPEN Drain
I, LVCMOS
I, LVCMOS
I, 4-LEVEL,
LVCMOS
I, 4-LEVEL,
LVCMOS
Clock output when loading EEPROM configuration, reverting to SMBus
clock input when EEPROM load is complete (ALL_DONE = 0).
External 2 kΩ to 5 kΩ pull-up resistor required as per SMBus interface
standards ⁽²⁾
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
open drain output.
External 2 kΩ to 5 kΩ pull-up resistor required as per SMBus interface
standards ⁽²⁾
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the
user set SMBus slave address inputs.
External 1 kΩ pull-up or pull-down recommended.
Note: In Pin Mode, AD2 must be tied via external 1 kΩ to GND.
A logic low on this pin starts the load from the external EEPROM⁽³⁾.
Once EEPROM load is complete (ALL_DONE = 0), this pin functionality
remains as READ_EN. It does not revert to an SD_TH input.
Reserved
For applications requiring Signal Detect status register read-back:
● Leave Pin 21 floating.
● Write Reg 0x08[2] = 1 if Pin 21 is floating.
Otherwise, tie Pin 21 via external 1 kΩ to GND (External 1 kΩ to VDD
(2.5 V mode) or VIN (3.3 V mode) is also acceptable).
Reserved
This input may be left floating, tied via 1 kΩ to VDD (2.5 V mode) or VIN
(3.3 V mode), or tied via 1 kΩ to GND.
I, 4-LEVEL,
LVCMOS
I, 4-LEVEL,
LVCMOS
I, 4-LEVEL,
LVCMOS
I, LVCMOS
I, 4-LEVEL,
LVCMOS
I, 4-LEVEL,
LVCMOS
EQA and EQB pins control the level of equalization for the A-channels
and B-channels, respectively. The pins are defined as EQA and EQB
only when ENSMB is de-asserted (low). Each of the four A-channels
have the same level unless controlled by the SMBus control registers.
Likewise, each of the four B-channels have the same level unless
controlled by the SMBus control registers.
When the device operates in Slave or Master Mode, the SMBus registers
independently control each lane, and the EQB pin is converted to an
AD3 input. See Table 4.
VODB[1:0] controls the output amplitude of the B-channels. The pins are
defined as VODB[1:0] only when ENSMB is de-asserted (low). Each of
the four B-channels have the same level unless controlled by the SMBus
control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane, and
VODB[1:0] pins are converted to AD0, AD1 inputs. See Table 5.
VODA[1:0] controls the output amplitude of the A-channels. The pins are
defined as VODA[1:0] only when ENSMB is de-asserted (low). Each of
the four A-channels have the same level unless controlled by the SMBus
control registers. When the device operates in Slave or Master Mode, the
SMBus registers provide independent control of each lane and the
VODA[1:0] pins are converted to SCL and SDA. See Table 5.
Reserved in Pin Mode (ENSMB = 0)
This input must be tied via external 1 kΩ to GND.
Controls the internal Signal Detect Status Threshold value when in Pin
Mode and SMBus Slave Mode. This pin is to be used for system
debugging only, as the signal detect threshold has no impact on the data
path. See Table 3 for more information.
For final designs, input can be left floating, tied via 1 kΩ to VDD (2.5 V
mode) or VIN (3.3 V mode), or tied via 1 kΩ to GND.
Reserved
Tie via external 1 kΩ to GND (External 1 kΩ to VDD (2.5 V mode) or VIN
(3.3 V mode) is also acceptable).
(3) When READ_EN is asserted low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to
an invalid or blank hex file, the DS80PCI810 waits indefinitely in an unknown state where SMBus access is not possible. ALL_DONE pin
remains high in this situation.
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