DS80PCI810 Datasheet, PDF (43/60 Pages) Texas Instruments – Low-Power 8 Gbps 8-Channel Linear Repeater

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Typical Applications (continued)
DS80PCI810
SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
Pattern
Generator
V_OD = 1.0 Vp-p,
DE = 0 dB
PRBS15
TL
Lossy Channel
IN DS80PCI810 OUT
Scope
BW = 60 GHz
Figure 9. Test Setup Connections Diagram
Pattern
Generator
V_OD = 1.0 Vp-p,
DE = -6 dB
PRBS15
TL1
Lossy Channel
IN DS80PCI810 OUT
TL2
Lossy Channel
Figure 10. Test Setup Connections Diagram
Scope
BW = 60 GHz
8.2.1.1 Design Requirements
As with any high speed design, there are many factors that influence the overall performance. Below are a list of
critical areas for consideration and study during design.
• Use 100 Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
The DS80PCI810 is designed to be placed at an offset location with respect to the overall channel attenuation. In
order to optimize performance, the repeater requires tuning to extend the reach of the cable or trace length while
also recovering a solid eye opening. To tune the repeater, the settings mentioned in Table 10 (for Pin Mode) and
Table 11 (for SMBus Modes) are recommended as a default starting point for most applications. Once these
settings are configured, additional tuning of the EQ and, to a lesser extent, VOD may be required to optimize the
repeater performance for each specific application environment.
Examples of the repeater performance as a generic high speed datapath repeater are illustrated in the
performance curves in the next section.
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