DS80PCI810 Datasheet, PDF (16/60 Pages) Texas Instruments – Low-Power 8 Gbps 8-Channel Linear Repeater

DS80PCI810
SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
www.ti.com
Device Functional Modes (continued)
PWDN ⁽¹⁾
(Pin 52)
0
0
0
0
1
RXDET
(Pin 22)
0
R
F
(Default)
1
X
Table 2. RX Detect Settings
SMBus REG
Bit[3:2]
00
01
10
11
X
INPUT
TERMINATION
Hi-Z
Pre Detect: Hi-Z
Post Detect: 50 Ω
Pre Detect: Hi-Z
Post Detect: 50 Ω
50 Ω
Hi-Z
RECOMMENDED
USE
COMMENTS
Manual Rx-Detect, input is Hi-Z
PCIe
Auto Rx-Detect, outputs test every 12 ms for 600
ms then stops; termination is Hi-Z until Rx
detection; once detected input termination is 50 Ω
Reset function by pulsing PWDN high for 5 µs then
low again
PCIe
Auto Rx-Detect, outputs test every 12 ms until
detection occurs; termination is Hi-Z until Rx
detection; once detected input termination is 50 Ω
Manual Rx-Detect, input is 50 Ω
Power Down mode, input is Hi-Z, output drivers
are disabled
Used to reset Rx-Detect State Machine when held
high for 5 µs
(1) In SMBus Slave Mode, the Rx Detect State Machine can be manually reset in software by overriding the device PRSNT function. This is
accomplished by setting the Override PRSNT bit (Reg 0x02[7]) and then toggling the PRSNT value bit (Reg 0x02[6]). See Table 9 for
more information about resetting the Rx Detect State Machine.
Table 3. Signal Detect Status Threshold Level⁽¹⁾⁽²⁾
LEVEL
1
2
3
4
SD_TH
(PIN 26)
0
R
F (default)
1
SMBus REG BIT[3:2]
and[1:0]
10
01
00
11
[3:2] ASSERT LEVEL
(mVp-p)
3 Gbps
12 Gbps
18
75
12
40
15
50
16
58
[1:0] DE-ASSERT LEVEL
(mVp-p)
3 Gbps
12 Gbps
14
55
8
22
11
37
12
45
(1) VDD = 2.5 V, 25°C, 1010 pattern at 1.5 Gbps and 101010 pattern at 12 Gbps
(2) Signal detect status threshold sets the value at which a signal detect status is flagged via SMBus Reg 0x0A. Regardless of the threshold
level, the output always remains enabled unless manually powered down.
7.4.3 SMBus Master Mode
When in SMBus Master Mode (ENSMB = Float), the VOD (output amplitude), equalization, and termination
disable features for multiple devices can be loaded via external EEPROM. By asserting a Float condition on the
ENSMB pin, an external EEPROM writes register settings to each device in accordance with its SMBus slave
address. The settings programmable by external EEPROM provide only a subset of all the register bits available
via SMBus Slave Mode, and the bit-mapping between SMBus Slave Mode registers and EEPROM addresses
can be referenced in Table 6. Once the EEPROM successfully finishes loading each device's register settings,
the device reverts back to SMBus Slave Mode and releases SDA/SCL control to an external master MCU. If the
EEPROM fails to load settings to a particular device, for example due to an invalid or blank hex file, the device
waits indefinitely in an unknown state where access to the SMBus lines is not possible.
7.4.4 Signal Conditioning Settings
Equalization and VOD settings accessible via the pin controls are chosen to meet the needs of most high speed
applications. These settings can also be controlled via the SMBus registers. Each pin input has a total of four
possible voltage level settings. Table 4 and Table 5 show both the Pin Mode and SMBus Mode settings that are
used in order to program the equalization and VOD gain for each DS80PCI810 channel.
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