DS80PCI810 Datasheet, PDF (46/60 Pages) Texas Instruments – Low-Power 8 Gbps 8-Channel Linear Repeater

DS80PCI810
SNLS493A – OCTOBER 2014 – REVISED JANUARY 2015
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Typical Applications (continued)
8.2.2 PCIe Board Applications (PCIe Gen-3)
The DS80PCI810 can be used to extend trace length on motherboards and line cards in PCIe Gen-3
applications. The high linearity of the DS80PCI810 aids in the link training protocol required by PCIe Gen-3 at 8
Gbps in accordance with PCI-SIG standards. For PCIe Gen-3, preservation of the pre-cursor and post-cursor Tx
FIR presets (P0-P10) is crucial to successful signal transmission from motherboard system root complex to line
card ASIC or Embedded Processor. Below is a typical example of the DS80PCI810 used in a PCIe application:
8
TX
Connector
8
RX
DS80PCI810
ASIC
or
PCIe EP
System Board
Root Complex
8
RX
DS80PCI810
Connector
8
TX
BoTarardce
Figure 21. Typical PCIe Gen-3 Configuration Diagram
8.2.2.1 Design Requirements
As with any high speed design, there are many factors that influence the overall performance. Please reference
Design Requirements in the Generic High Speed Repeater application section for a list of critical areas for
consideration and study during design.
8.2.2.2 Design Procedure
In PCIe Gen-3 applications, there is a large range of flexibility regarding the placement of the DS80PCI810 in the
signal path due to the high linearity of the device. If the PCIe slot must also support lower speeds like PCIe Gen-
1 (2.5 Gbps) and Gen-2 (5.0 Gbps), it is recommended to place the DS80PCI810 closer to the endpoint Rx.
Once the DS80PCI810 is placed on the signal path, the repeater must be tuned. To tune the repeater, the
settings mentioned in Table 10 (for Pin Mode) and Table 11 (for SMBus Modes) are recommended as a default
starting point for most applications. Once these settings are configured, additional tuning of the EQ and, to a
lesser extent, VOD may be required to optimize the repeater performance to pass link training preset
requirements for PCIe Gen-3.
An example of a test configuration used to evaluate the DS80PCI810 in this application can be seen in
Figure 22. For more information about DS80PCI810 PCIe applications, please refer to application note SNLA227.
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