TL16C752CI-Q1_16 Datasheet, PDF (5/57 Pages) Texas Instruments – Dual UART

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TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
Pin Functions (continued)
PIN
TYPE
NAME
NO.
DESCRIPTION
A2
26
I Address bit 2 select. Internal registers address selection. Refer to Figure 26 for register address map.
CDA
CDB
40
16
I
Carrier detect (active low). These inputs are associated with individual UART channels A and B. A
low on these pins indicates that a carrier has been detected by the modem for that channel.
CSA
CSB
10
Chip select A and B (active low). These pins enable data transfers between the user CPU and the
I TL16C752CI-Q1 for the channel or channels addressed. Individual UART sections (A and B) are
11
addressed by providing a low on the respective CSA and CSB pin.
CTSA
CTSB
38
Clear to send (active low). These inputs are associated with individual UART channels A and B. A
low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
I TL16C752CI-Q1 device. Status can be checked by reading MSR[4]. These pins only affect the
23
transmit and receive operations when auto CTS function is enabled through the enhanced feature
register (EFR[7]), for hardware flow control operation.
D0
44
D1
45
D2
46
D3
47
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or
I/O from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive
D4
48
serial data stream.
D5
1
D6
2
D7
3
DSRA
DSRB
39
Data set ready (active low). These inputs are associated with individual UART channels A through B.
I A low on these pins indicates the modem or data set is powered on and is ready for data exchange
20
with the UART.
DTRA
DTRB
34
Data terminal ready (active low). These outputs are associated with individual UART channels A
through B. A low on these pins indicates that the TL16C752CI-Q1 is powered on and ready. These
35
O
pins can be controlled through the modem control register. Writing a 1 to MCR[0] sets the DTR output
to low, enabling the modem. The output of these pins is high after writing a 0 to MCR[0], or after a
reset. These pins can also be used in the RS-485 mode to control an external RS-485 driver or
transceiver.
GND
17
Pwr Power signal and power ground
INTA
INTB
30
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA-B. INTA-B are
enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt enable register (IER) and
O when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver
29
buffer data, transmit buffer empty, or when a modem status flag is detected. INTA-B are in the high-
impedance state after reset.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal register
IOR
19
I defined by address bits A0 through A2 onto the TL16C752CI-Q1 device data bus (D0 through D7) for
access by an external CPU.
IOW
Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0
15
I through D7) from the external CPU to an internal register that is defined by address bits A0 through
A2.
NC
12
NC
24
— No internal connection
NC
25
NC
37
OPA
OPB
32
User defined outputs. This function is associated with individual channels A and B. The state of these
pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to
O active mode and OP to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the 3-state
9
mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit
3). The output of these two pins is high after reset.
RESET
Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the
36
I receiver input are disabled during reset time. For initialization details, see TL16C752CI-Q1 device
external reset conditions. RESET is an active high input.
RIA
41
Ring indicator (active low). These inputs are associated with individual UART channels A and B. A
RIB
21
I
logic low on these pins indicates the modem has received a ringing signal from the telephone line. A
low-to-high transition on these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the modem status register (MSR).
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