TL16C752CI-Q1_16 Datasheet, PDF (45/57 Pages) Texas Instruments – Dual UART

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9 Application and Implementation
TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The typical implementation is to use the TL16C752CI-Q1 as a dual RS-232 interface, which is intended to
operate with a 5-V microprocessor.
9.2 Typical Application
Voltage
Regulator
Microcontroller
Data
Address
IOW, IOR, Reset
Chip Select
Int and RDY
TL16C752C
UART Ch 1
MAX232
UART Ch 2
MAX232
XTAL1
XTAL2 (optional)
Crystal/
Oscillator
1.8432 MHz
Figure 39. Typical Application Dual RS-232 Interface
9.2.1 Design Requirements
Include the recommended operating conditions for 3.3 V provided by the controller board, but with the input clock
equal to 1.8432 MHz, and include the Operating free-air temperature conditions. The controller must have two 8-
bit ports, one for the control signals and another for the I/O data. A third port is optional to monitor the
interruptions and TX/RX ready signals (if it is needed).
9.2.2 Detailed Design Procedure
1. Implement the schematic as is shown in Figure 39.
2. Implement on the controller the READ and WRITE routines to meet the timing requirements of the Timing
Requirements, use Figure 1 and Figure 2 as a guideline.
3. Initialize all the configuration registers. TI recommends not to obviate the default settings and initialize all of
the set of configuration registers. The base set of registers that are used during high-speed data transfer
have a straightforward access method. The extended function registers require special access bits to be
decoded along with the address lines. The following guide helps with programming these registers. Note that
the descriptions are for individual register access. Some streamlining through interleaving can be obtained
when programming all the registers.
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