TL16C752CI-Q1_16 Datasheet, PDF (16/57 Pages) Texas Instruments – Dual UART

TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
8 Detailed Description
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8.1 Overview
The TL16C752CI-Q1 UART is pin-compatible with the ST16C2550 UART in the PFB package. It provides more
enhanced features. All additional features are provided through a special enhanced feature register.
The TL16C752CI-Q1 UART will perform serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The
complete status of each channel of the TL16C752CI-Q1 UART can be read at any time during functional
operation by the processor.
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and
transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.
8.2 Functional Block Diagram
A2 to A0
D7 to D0
CSA
CSB
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
RXRDYA
RXRDYB
RESET
XTAL1
XTAL2
Data Bus
Interface
Crystal
Oscillator
Buffer
UART Channel A
64-Byte TX FIFO ^TX
UART Regs
Baud
Rate
Generator
64-Byte RX FIFO
RX
UART Channel B
64-Byte TX FIFO ^TX
UART Regs
Baud
Rate
Generator
64-Byte RX FIFO
RX
TXA
CTSA
OPA, DTRA
DSRA, RIA, CDA
RTSA
RXA
TXB
CTSB
OPB, DTRB
DSRB, RIB, CDB
RTSB
RXB
V_CC
GND
Figure 14. TL16C752CI-Q1 Functional Block Diagram
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