TL16C752CI-Q1_16 Datasheet, PDF (12/57 Pages) Texas Instruments – Dual UART

TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
RX (A–B)
INT (A–B)
IOR
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
5 Data Bits
6 Data Bits
7 Data Bits
Parity
Bit
Next
Data
Start
Bit
t_20d
Active
t_21d
Active
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RX (A–B)
RXRDY (A–B)
RXRDY
IOR
RX (A–B)
RXRDY (A–B)
RXRDY
IOR
16-Baud Rate Clock
Figure 4. Receive Timing
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Next
Data
Start
Bit
t_25d
Active
Data
Ready
t_26d
Active
Figure 5. Receive Ready Timing in Non-FIFO Mode
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
First Byte
That Reaches
The Trigger
Level
t_25d
Active
Data
Ready
t_26d
Active
Figure 6. Receive Timing in FIFO Mode
12
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