TL16C752CI-Q1_16 Datasheet, PDF (33/57 Pages) Texas Instruments – Dual UART

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TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
8.5.5 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are
selected by writing the appropriate bits to the LCR. Table 9 shows line control register bit settings.
Table 9. LCR Bit Settings
BIT
BIT SETTINGS
Specifies the word length to be transmitted or received
00 – 5 bits
1:0
01 – 6 bits
10 − 7 bits
11 – 8 bits
Specifies the number of stop bits:
2
0 – 1 stop bits (Word length = 5, 6, 7, 8)
1 – 1.5 stop bits (Word length = 5)
1 – 2 stop bits (Word length = 6, 7, 8) 3
3
0 = No parity
1 = A parity bit is generated during transmission and the receiver checks for received parity.
4
0 = Odd parity is generated (if LCR[3] = 1)
1 = Even parity is generated (if LCR[3] = 1)
Selects the forced parity format (if LCR(3) = 1)
5
If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data.
If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received data.
Break control bit
6
0 = Normal operating condition
1 = Forces the transmitter output to go low to alert the communication terminal.
7
0 = Normal operating condition
1 = Divisor latch enable
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