TL16C752CI-Q1_16 Datasheet, PDF (38/57 Pages) Texas Instruments – Dual UART

TL16C752CI-Q1
SLLSEQ9A – OCTOBER 2015 – REVISED FEBRUARY 2016
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8.5.12 Divisor Latches (DLL, DLH)
Two 8-bit registers store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH,
stores the most significant part of the divisor. DLL stores the least significant part of the division.
DLL and DLH can only be written to before sleep mode is enabled (that is, before IER[4] is set).
8.5.13 Transmission Control Register (TCR)
This 8-bit register is used to store the receive FIFO threshold levels to start or stop transmission during hardware
or software flow control. Table 17 shows transmission control register bit settings.
Table 17. TCR Bit Settings
BIT
BIT SETTINGS
3:0
RCV FIFO trigger level to HALT transmission (0 to 60)
7:4
RCV FIFO trigger level to RESTORE transmission (0 to 60)
TCR trigger levels are available from 0 to 60 bytes with a granularity of four.
TCR can be written to only when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that
TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must
be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious
operation of the device.
8.5.14 Trigger Level Register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 18 shows trigger level
register bit settings.
Table 18. TLR Bit Settings
BIT
BIT SETTINGS
3:0
Transmit FIFO trigger levels (4 to 60), number of spaces available
7:4
RCV FIFO trigger levels (4 to 60), number of characters available
TLR can be written to only when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are 0, then the selectable
trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels.
Trigger levels from 4 to 60 bytes are available with a granularity of 4. The TLR should be programmed for N / 4,
where N is the desired trigger level.
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