LP3907-Q1 Datasheet, PDF (5/53 Pages) Texas Instruments – Dual High-Current Step-Down DC-DC And Dual Linear Regulator

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LP3907-Q1
SNVSA55A – DECEMBER 2014 – REVISED MAY 2015
WQFN
NUMBER
1
2
PIN
DSBGA
NUMBER
B4, B5
C4
NAME
VINLDO12
EN_T
3
C3
nPOR
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DAP
C5
GND_SW1
D5
SW1
E5
VIN1
D4
ENSW1
E4
FB1
D3
GND_C
E3
AVDD
E2
FB2
D2
ENSW2
E1
VIN2
D1
SW2
C1
GND_SW2
C2
SDA
B2
SCL
B1
GND_L
A1
VINLDO1
A2
LDO1
B3
ENLDO1
A3
ENLDO2
A4
LDO2
A5
VINLDO2
DAP
Pin Functions
I/O
TYPE ⁽¹⁾
DESCRIPTION
I
I
O
G
O
I
I
I
G
I
I
I
I
O
G
I/O
I
G
I
O
I
I
O
I
GND
PWR
D
D
G
PWR
PWR
D
A
G
PWR
A
D
PWR
PWR
G
D
D
G
PWR
PWR
D
D
PWR
PWR
GND
Analog Power for Internal Functions (VREF, BIAS, I²C, Logic)
Enable for preset power on sequence. (See .)
nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic
output 100-kΩ pull-up resistor. nPOR is pulled to ground when the
voltages on these supplies are not good. See Flexible Power-On Reset
(Power Good with Delay) section for more info.
Buck1 NMOS Power Ground
Buck1 switcher output pin
Power in from either DC source or Battery to Buck1
Enable Pin for Buck1 switcher, a logic HIGH enables Buck1
Buck1 input feedback terminal
Non switching core ground pin
Analog Power for Buck converters
Buck2 input feedback terminal
Enable Pin for Buck2 switcher, a logic HIGH enables Buck2
Power in from either DC source or Battery to Buck2
Buck2 switcher output pin
Buck2 NMOS Power ground
I²C Data (bidirectional)
I²C Clock
LDO ground
Power in from either DC source or battery to input terminal to LDO1
LDO1 Output
LDO1 enable pin, a logic HIGH enables the LDO1
LDO2 enable pin, a logic HIGH enables the LDO2
LDO2 Output
Power in from either DC source or battery to input terminal to LDO2.
Connection isn't necessary for electrical performance, but it is
recommended for better thermal dissipation.
(1) A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin.
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