LP3907-Q1 Datasheet, PDF (41/53 Pages) Texas Instruments – Dual High-Current Step-Down DC-DC And Dual Linear Regulator

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LP3907-Q1
SNVSA55A – DECEMBER 2014 – REVISED MAY 2015
As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the
minimum value given in the recommended capacitor specifications table. Note that the graph shows the
capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended
that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions,
as some capacitor sizes (for example, 0402) may not be suitable in the actual application.
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a
similar tolerance over a reduced temperature range of −55°C to 85°C. Many large value ceramic capacitors,
larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R is recommended over Z5U and
Y5V in applications where the ambient temperature changes significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.
9.2.2.2.4 Input Capacitor Selection for SW1 And SW2
A ceramic input capacitor of 10 µF, 6.3 V is sufficient for the magnetic DC-DC converters. Place the input
capacitor as close as possible to the input of the device. A large value may be used for improved input voltage
filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias
characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The
input filter capacitor supplies current to the PFET switch of the DC-DC converter in the first half of each cycle
and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR (Equivalent
Series Resistance) provides the best noise filtering of the input voltage spikes due to fast current transients. A
capacitor with sufficient ripple current rating should be selected. The Input current ripple can be calculated as:
I_rms = I_outmax
V_OUT
V_IN
§ ^r2 ·
© ^{1 +} 12¹ ^where
r = ^{(Vin ± Vout) x Vout}
L x f x I_outmax x V_in
(8)
The worse case is when V_IN = 2 V_OUT.
9.2.2.2.5 Output Capacitor Selection for SW1, SW2
A 10-μF, 6.3-V ceramic capacitor should be used on the output of the SW1 and SW2 magnetic DC-DC
converters. The output capacitor needs to be mounted as close as possible to the output of the device. A large
value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V
type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when
selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC
bias curves should be requested from them and analyzed as part of the capacitor selection process.
The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the
load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.
These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these
functions.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
ESR and can be calculated as follows:
I_ripple
V_pp-c = _{4 x f x C}
(9)
Voltage peak-to-peak ripple due to ESR can be expressed as follows:
V_PP–ESR = 2 × I_RIPPLE × R_ESR
(10)
Because the V_PP-C and V_PP-ESR are out of phase, the rms value can be used to get an approximate value of the
peak-to-peak ripple:
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