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| LP3907-Q1 Datasheet, PDF (21/53 Pages) Texas Instruments – Dual High-Current Step-Down DC-DC And Dual Linear Regulator | |||
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www.ti.com
LP3907-Q1
SNVSA55A â DECEMBER 2014 â REVISED MAY 2015
Table 6. Power-Off Timing Specification
DESCRIPTION
t1
Programmable Delay from EN_T deassertion to VCC_Buck1 Off
t2
Programmable Delay from EN_T deassertion to VCC_Buck2 Off
t3
Programmable Delay from EN_T deassertion to VCC_LDO1 Off
t4
Programmable Delay from EN_T deassertion to VCC_LDO2 Off
MIN
NOM
MAX UNIT
1.5
ms
2
ms
3
ms
6
ms
8.3.3 Flexible Power-On Reset (Power Good with Delay)
The LP3907-Q1 is equipped with an internal Power-On-Reset (POR) circuit which monitors the output voltage
levels on Bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck
outputs are below 91% of the rising value , or when one or both outputs fall below 82% of the desired value. The
time delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms) 50 ms by
default. The system designer can choose the external pull-up resistor (that is, 100 kâ¦) for the nPOR pin.
Copyright © 2014â2015, Texas Instruments Incorporated
Product Folder Links: LP3907-Q1
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