LP3907-Q1 Datasheet, PDF (42/53 Pages) Texas Instruments – Dual High-Current Step-Down DC-DC And Dual Linear Regulator

LP3907-Q1
SNVSA55A – DECEMBER 2014 – REVISED MAY 2015
www.ti.com
V_pp-rms = V_pp-c2 + V_pp-esr2
(11)
Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series
resistance of the output capacitor (R_ESR). The R_ESR is frequency dependent as well as temperature dependent.
The R_ESR should be calculated with the applicable switching frequency and ambient temperature.
CAPACITOR
C_LDO1
C_LDO2
C_SW1
C_SW2
Table 9. Suggested Capacitor Values
MIN VALUE (µF)
0.47
0.47
10
10
DESCRIPTION
LDO1 output capacitor
LDO2 output capacitor
SW1 output capacitor
SW2 output capacitor
RECOMMENDED TYPE
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
9.2.2.2.6 I²C Pull-Up Resistor
Both SDA and SCL terminals need to have pull-up resistors connected to VINLDO12 or to the power supply of
the I²C master. The values of the pull-up resistors (typical approximately 1.8 kΩ) are determined by the
capacitance of the bus. Too large of a resistor combined with a given bus capacitance results in a rise time that
would violate the max. rise time specification. A too-small resistor results in a contention with the pull-down
transistor on either slave(s) or master.
9.2.2.3 Operation Without I²C Interface
Operation of the LP3907-Q1 without the I²C interface is possible if the system can operate with default values for
the LDO and Buck regulators (see Factory Programmable Options.) The I²C-less system must rely on the correct
default output values of the LDO and Buck converters.
9.2.2.3.1 High V_IN High-Load Operation
Additional information is provided when the IC is operated at extremes of V_IN and regulator loads. These are
described in terms of the Junction temperature and, Buck output ripple management.
9.2.2.3.2 Junction Temperature
The maximum junction temperature T_J-MAX-OP of 125°C of the IC package.
Equation 12 through Equation 17 demonstrate junction temperature determination, ambient temperature T_A-MAX,
and total chip power must be controlled to keep T_J below this maximum:
T_J-MAX-OP = T_A-MAX + (R_θJA) [°C/ Watt] × (P_D-MAX) [Watts]
(12)
Total IC power dissipation P_D-MAX is the sum of the individual power dissipation of the four regulators plus a minor
amount for chip overhead. Chip overhead is Bias, TSD, and LDO analog.
P_D-MAX = P_LDO1 + P_LD02 + P_BUCK1 + P_BUCK2 + (0.0001A × V_IN) [Watts].
(13)
Power dissipation of LDO1:
P_LDO1 = (V_INLDO1 – V_OUTLDO1) × I_OUTLDO1 [V × A]
(14)
Power dissipation of LDO2:
P_LDO2 = (V_INLDO2 – V_OUTLDO2) × I_OUTLDO2 [V × A]
(15)
Power dissipation of Buck1:
P_Buck1 = P_IN – P_OUT = V_OUTBuck1 × I_OUTBuck1 × (1 – η₁) / η₁ [V × A]
where
• η₁ = efficiency of buck 1
(16)
Power dissipation of Buck2:
P_Buck2 = P_IN – P_OUT = V_OUTBuck2 × I_OUTBuck2 × (1 – η₂) / η₂ [V × A]
where
• η₂ = efficiency of Buck2
42
Submit Documentation Feedback
Product Folder Links: LP3907-Q1
Copyright © 2014–2015, Texas Instruments Incorporated