LP3907-Q1 Datasheet, PDF (45/53 Pages) Texas Instruments – Dual High-Current Step-Down DC-DC And Dual Linear Regulator

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11.2 Layout Example
LP3907-Q1
SNVSA55A – DECEMBER 2014 – REVISED MAY 2015
Figure 49. LP3907-Q1 DSBGA Layout Example
11.3 Thermal Considerations of WQFN Package
The LP3907-Q1 is a monolithic device with integrated power FETs. For that reason, it is important to pay special
attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize
power dissipation of the WQFN package.
The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at
the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.
Compared to the traditional leaded packages where the die attach pad is embedded inside the molding
compound, the WQFN reduces one layer in the thermal path.
The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered
down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on
thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (R_θJA) can be improved by a
factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land
and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer
diameter for thermal vias are 1.27 mm and 0.33 mm, respectively. Typical copper via barrel plating is 1 oz,
although thicker copper may be used to further improve thermal performance. The LP3907-Q1 die attach pad is
connected to the substrate of the IC, and therefore, the thermal land and vias on the PCB board need to be
connected to ground (GND pin).
For more information on board layout techniques, refer to Application Note AN–1187 Leadless Lead Frame
Package (LLP) (SNOA401) on http://www.ti.com. This application note also discusses package handling, solder
stencil, and the assembly process.
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